(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a polycide, (metal silicide-polysilicon), gate structure, for a semiconductor device.
(2) Description of the Prior Art
The use of self-aligned contact, (SAC), structures, have allowed smaller area, source/drain regions to be used for metal oxide semiconductor field effect, (MOSFET), devices. The SAC structures, formed in openings that were created, self-aligned to a silicon nitride encapsulated, gate structure, result in metal contact to a borderless, source/drain region, eliminating the need of opening a fully landed contact hole, in an insulator layer, to the source/drain region. The replacement of the area consuming, non-borderless, source/drain contact hole opening, with a SAC opening, has allowed a reduction of source/drain area to be realized, thus resulting in smaller, higher performing MOSFET devices, with decreased source/drain to substrate capacitance, to be obtained.
The use of polycide gate structures, comprised of an overlying metal silicide layer, such as tungsten silicide, on an underlying polysilicon layer, can however present difficulties during an oxidation procedure, used as to form the sidewall oxide component, of the composite insulator spacers, on the sides of the polycide gate structure. Prior to forming a silicon nitride spacer, needed for the subsequent, selective, SAC opening procedure, an oxidation procedure is used to create the sidewall oxide layer, on the sides of the polycide gate structure. The faster growth of an oxide layer, on the exposed sides of the tungsten silicide layer, compared to the slower growth of an oxide layer, on the exposed sides of the polysilicon layer, can result in a sidewall oxide profile, with the thicker oxide layer protruding from the sides of the tungsten silicon layer. This profile can present difficulties, or a failure mechanism, during the subsequent, selective SAC opening procedure. For example the thicker oxide layer, butting out from the sides of the tungsten silicide layer, transfers to a conformal butting out, of an overlying silicon nitride layer, also used as a component of the composite insulator spacer. The anisotropic reactive ion etching, (RIE), procedure, used to finalize the composite insulator spacers, can remove the regions of silicon nitride exposed in an area in which the overlying silicon nitride protruded from the underlying thicker oxide layer, even resulting in exposure of the underlying sidewall oxide layer, via complete removal of silicon nitride in this region. The subsequent SAC opening, performed to selectively remove silicon oxide regions, can then attack the exposed sidewall oxide layer, resulting in gate to source/drain shorts, when interfaced by the SAC contact structure.
This invention will describe a solution to the undesirable sidewall oxide profile, resulting from the oxidation of a tungsten silicidexe2x80x94polysilicon, polycide gate structure. A selective wet etch solution, is used to laterally recess the tungsten silicide layer, allowing the thicker sidewall oxide layer, to be contained in the recessed region of the tungsten silicide layer, resulting in a smooth, non-protruding composite insulator layer. After deposition of a silicon nitride layer, and anisotropic RIE sidewall procedures, a non-defective, composite insulator layer results, allowing a successful SAC opening to be performed. Prior art, such as Fakuda, in U.S. Pat. No. 5,698,072, describes a process in which a top portion of a metal silicide layer is isotopically recessed, via a dry etching procedure. However that invention does not offer the lateral recess, of the entire metal silicide layer, via a wet etch procedure, followed by the growth of a thick oxide layer, entirely contained in the lateral recess, and overlaid with a silicon nitride layer, resulting in a subsequent composite insulator spacers, on the sides of a polycide gate structure, comprised of an overlying silicon nitride layer, and an underlying oxide layer, featuring a portion of the oxide layer, located in the lateral recess in the tungsten silicide layer.
It is an object of this invention to form a straight walled, silicon nitride capped, polycide gate structure, comprised of tungsten silicide, on polysilicon, via an anisotropic RIE procedure, followed by a isotropic wet etch procedure, used to laterally recess the tungsten silicide layer, with the lateral recess located between an overlying capping, silicon nitride layer, and the underlying polysilicon layer.
It is another object of this invention to grow a silicon oxide, sidewall layer, on the exposed sides of the polycide gate structure, with a thicker silicon oxide layer forming on the sides of the laterally recessed tungsten silicide layer, and a thinner silicon oxide layer forming on the exposed sides of the polysilicon layer.
It is still another object of this invention to deposit a silicon nitride layer, and via anisotropic RIE procedures, create composite insulator spacers, comprised of silicon nitride, overlying the thick silicon oxide component, located on the sides of the laterally recessed tungsten silicide layer, and overlying the thin silicon oxide layer, located on the sides of the polysilicon layer.
In accordance with the present invention a method is described for fabricating a MOSFET device, with composite insulator spacers, on the sides of a polycide gate structure, with the composite insulator spacers comprised of a silicon nitride layer, on a thick silicon oxide component of a silicon oxide sidewall layer, located on the sides of a laterally recessed tungsten silicide layer, and on a thin silicon oxide component, located on the sides of a polysilicon layer. A silicon nitride capped, polycide gate structure, comprised of a silicon nitride capping layer, a tungsten silicide layer, and a polysilicon layer, is formed via an anisotropic RIE procedure, on an underlying gate insulator layer. After creation of lightly doped source/drain regions, in an area of the semiconductor substrate, not covered by the silicon nitride capped, polycide gate structure, an isotropic wet etch procedure, is performed to selectively, create a lateral recess in the tungsten silicide layer, with the lateral recess located between the overlying, capping silicon nitride layer, and the underlying polysilicon layer. An oxidation procedure is used to grow the silicon oxide sidewall oxide layer, of the composite insulator spacer, comprised of a thick silicon oxide component, located on the sides of the laterally recessed, tungsten silicide layer, filling the recess, and a thinner silicon oxide component, formed on the exposed sides of the polysilicon layer. A silicon nitride layer is next deposited, followed by an anisotropic RIE procedure, resulting in the composite insulator spacers, comprised of an overlying silicon nitride layer, overlying a silicon oxide sidewall layer, comprised of a thick silicon oxide component, on the sides of the laterally recessed, tungsten suicide layer, and a thinner silicon oxide component, on the sides of the polysilicon layer. After formation of heavily doped source/drain regions, an interlevel silicon oxide layer is deposited, followed by creation of a SAC opening, in the interlevel silicon oxide layer, exposing a heavily doped source/drain region. The SAC opening, allowing a subsequent fully landed SAC structure to be formed on the heavily doped source/drain region, was selectively formed in the interlevel silicon oxide layer, using the silicon nitride capping layer, and the silicon nitride component of the composite insulator spacers, as etch stops.